Obstacle-Aware Length-Matching Bus Routing Using Rectangular Pattern Detouring

碩士 === 中華大學 === 資訊工程學系(所) === 98 === As technology becomes more advanced, the functions in many processors become enhanced and the clock frequency increases. The complexity in an integrated circuit increases gradually, and delays of all the signals on PCBs are requested to meet the timing constraint...

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Bibliographic Details
Main Authors: Jhong, Ming-Ching, 鍾明清
Other Authors: Yan, Jin-Tai
Format: Others
Language:zh-TW
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/11831341847482081928
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Summary:碩士 === 中華大學 === 資訊工程學系(所) === 98 === As technology becomes more advanced, the functions in many processors become enhanced and the clock frequency increases. The complexity in an integrated circuit increases gradually, and delays of all the signals on PCBs are requested to meet the timing constraints with very high accuracy. Generally speaking, the length of a single net on PCBs decides the delay of the net. Under the consideration of the manufacture cost, the routing area on PCBs must be minimized. Hence, the challenge of routing thousands of nets in a very limited area becomes an important issue. In this paper, based on the concept of rectangular pattern detouring and the analysis of unreachable grids in the rectangular pattern detouring, an efficient O(mnlog(mn)) algorithm is proposed to generate the longest path between two terminals in routing grids with obstacles. Furthermore, given a set of nets in a bus on routing grids with obstacles, and the length constraints for all the nets in the bus, based on this proposed longest path generation, all the nets in the bus can be assigned onto a given set of routing grids to satisfy the length constraints for obstacle-aware length-matching bus routing. Compared to the CAFÉ router [19], our approach complete the routing process of all the nets in the bus and match the length constraints more accuracy as the result of experiment show.