Design of pulse width control loops

• Main Authors: Yong De You, 游永得
• Other Authors: S. K. Kao
• Format: Others
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/26478854632150134614

碩士 === 長庚大學 === 電機工程學系 === 98 === As the process advances, the circuit affected by the decline in operating voltage, temperature, process ariation effects are increasingly severe, in order to suppress these variations impact on the circuit, while the use of feedback control mechanisms to stabilize the system output clock work cycle, this paper for the pulse width control loop circuit (PWCL), it puts forward to reduce jitter and improve the efficiency of the method, this paper is divided into three parts.The first part of the pulse width control circuit for the control-level voltage signals for controlling the changes in a very sensitive issue and propose solutions, if the system at the same operating frequency, the control voltage signal of the voltage ripple greater, the output when the clock signal jitter (Jitter) will be greater this problem in the advanced manufacturing process would be more serious, so provide a way to achieve the reduction of voltage with waves, and thus to reduce the output clock jitter effects. For the second part, it is provided in the literature for the frequency and duty cycle detection circuit to do improvements, making the whole circuit can provide a better operational performance. The third part, in the pulse width control loop functions, in addition to the original duty cycle correction, but also increased the clock signal drive capability to enhance functionality.