Fluorinated CMOS HfO2 n-/p-MOSFETS by Pre- and Post-CF4 Plasma Passivation for High Performance (HP) and Low Stand-by Power (LSTP) Application

• Main Authors: Huai Hsien Chiu, 邱懷賢
• Other Authors: C. S. Lai
• Format: Others
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/49564918928638807084

碩士 === 長庚大學 === 電子工程學系 === 98 === In this study, Fermi-level pinning (FLP) free and relaxation of negative-bias temperature-instability (NBTI) for fluorinated zero interfacial layer (Z-IL) HfO2 CMOS were achieved by CF4 plasma treatment on Si substrate. 48% and 45% driving current enhancement were obtained for n-MOSFET and p-MOSFET, respectively (threshold voltage decrease~210mV due to FLP free). For the fluorinated samples, low binding energy Hf–Si peaks (14.3~16.7eV) were disappeared and replaced by strong Hf–F bonding (19.5~21.6eV). The fluorine (F) incorporation was responsible for the reduction of the amount of Si participating in Hf-silicate formation and suppression of interface-reaction (oxygen diffusion) to result in Z-IL. A new Z-IL formation and low oxygen vacancy mechanism was established. This Z-IL with F accumulation improved the Fermi level pinning shift from ~0.1eV to ~0.02eV in high temperature treatment. For the reliability stressing, NBTI, the Vth shifts were relaxed 0.62 V due to the released-fluorine re-incorporating and passivating the shallow traps in the HfO2 bulk. The CF4 plasma treatment on Si substrate process is compatible with 22 nm CMOS technology and beyond.