| Summary: | 碩士 === 長庚大學 === 電子工程學系 === 98 === A high gain Ka-band CMOS Low-Noise-Amplifier is proposed in this paper. The CMOS LNA based on 4 stages common source structure. In each stage was connected by Stacked-Grounded-Coplanar-Waveguide transmission line structure in a TSMC 0.18-μm CMOS technology to reduce the loss from silicon substrate. The design of two stages noise matching increases the noise isolation between the gain matching stages and noise matching stages. The power gain of the LNA is higher than 20dB from 30GHz to 34GHz with 4GHz band width. The measured noise about 7dB from 30Ghz-34GHz. The power consumption of the LNA is only 40 mW.
in order to enhance the RF performance of CMOS devices, this thesis is the first to demonstrate the field-plate (FP) Dual Gate technology into the 0.09-μm CMOS devices, for improvement in the devices’ linearity, noise, gain, and output power. The main propose of FP technology is to reduce the electric field between gate and drain terminals. It forms a FP-induced depletion region and reduces the leakage current simultaneously, to improve the linearity and power performance for CMOS devices.
The Ka band power amplifier based on the compact microstrip resonator cell(CMRC). In this technology, we can improve the linearity lightly. in this thesis, we described the detail of the amplifier.
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