| Summary: | 碩士 === 長庚大學 === 資訊工程學研究所 === 98 === Power reduction is a very important issue in hardware chip design, especially when the area of a chip becomes small and small but the operations on a chip become more and more. Previous studies proposed data flow graph (DFG) scheduling algorithms to reduce a chip’s peak power consumption or average power consumption. However, they have not considered the problem of power consumption stabilization. The power consumption stabilization means that the power consumption of a chip can be stabilized in a range, such that the power supply can supply steady power to this chip during the chip’s working time. If we can do so, not only the system reliability can be improved, but also the energy consumption can be reduced. In this thesis, we will propose a power consumption stabilization mechanism. In this mechanism, we will use the dynamic voltage scaling (DVS) technique to adjust a chip’s supply voltage when it executes a power-hungry operation, like Multiply, and use DFG scheduling algorithm to schedule the execution sequence of total operations for this chip. The goal of the mechanism is to stabilize the power consumption of the chip in an as minimal as possible range such that the requirements of total energy consumption and performance of the chip can be satisfied. The problem of the power consumption stabilization can be modeled as an Integer Linear Programming (ILP) problem. That is, the goal of above mechanism can be represented as an objective function, under a set of “real-world” constraints, e.g., the hardware resource constraint. Through ILP modeling, we can find the optimal solution to minimize the objective function; i.e., we can find the optimal power-stabilization scheduling for a DFG. The time complexity to find the optimal solution, however, is very high. To resolve it, we will propose a heuristic algorithm to find the approximated solution to achieve our goal. The disadvantage of this algorithm is that it will increase a little execution time (delayed control step in the DFG) to solve the problem. That is, our heuristic algorithm is more suitable for soft real- time systems. In the experiment, we use five different benchmarks to compare the performance of the proposed heuristic algorithm. We first transfer the operation sequence in those benchmarks into the DFGs. Then we apply the ILP model to find the optimal solutions for these DFGs. Also, we will use the heuristic algorithm to find their approximated solutions. The results show that when each type of operations evenly distributed in a DFG, our heuristic algorithm can find the scheduling as optimal as it in the ILP model. But when the DFG has more complex operations falling on the critical path, the heuristic algorithm can still find the approximated solution, compared with the optimal one in the ILP model.
|
|---|
