A Low Power Sigma Delta Modulator with CML Inverter

• Main Authors: Chuang-shun Xu, 徐創順
• Other Authors: Shuenn-Yuh Lee
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/94497943717672370694

碩士 === 國立中正大學 === 電機工程所 === 98 === An operational amplifier (OPAMP) is the most important device and consumes the most of power in a switch-capacitor (SC) sigma-delta modulator (SDM), but it is hard to design OPAMPs in modern low voltage CMOS technologies. Because of the lower supply voltage resulted in new technologies, which makes the analog circuits are difficult to design. In order to overcome this issue, this thesis adopts a current-mode logic (CML) circuit to replace the OPAMP and implement a SDM. The SDM presented in this thesis is employed in global system for mobile communication/enhanced data rates for GSM evolution (GSM/EDGE), the required signal bandwidth is 250 kHz, and the effective numbers of bits (ENOB) are over 10 bits. In order to determine the circuit specifications, the behavioral models with non-ideal effects are developed and applied to the third-order low-pass SDM architecture. The SDM is implemented in TSMC 0.18 μm 1P6M CMOS process and has the sampling frequency of 16.384 MHz, a signal bandwidth of 256 kHz, an OSR of 32. The measured results reveal the SNR and SNDR are 65 dB and 64.5 dB, respectively. The total power dispassion is 0.33 mW under the digital supply voltage of 1.45 V and analog supply voltage of 1 V, respectively.