| Summary: | 碩士 === 國立中正大學 === 電機工程所 === 98 === This thesis points out the problems of transition power consumption in various function units within a microprocessor. To discuss and reduce the problems, we propose a low power manageable system named Power Block Manager(PBM).
The concept of Power Block Manager is to view every function block as an independent object, however, when the system is under running, many of them are work with nothing. To stop running those function units will not affect the output results, besides, it can save many dynamic power dissipation.
The proposed PBM architecture divides in three parts. The first is instruction type detector, it is responsible for transforming the instruction into low power system’s class types. The second part is a power block table, you can call it a on/off table. This table will point out each power blocks whether it should turn on or off according to the instruction type. The last is the scheduling part, queuing the power control signals to meet the pipelining system in case it occurs “Data Hazard” and
results in system crash.
|
|---|
