| Summary: | 博士 === 國立中正大學 === 資訊工程所 === 98 === In this dissertation, a high performance AVS/H.264 dual mode video decoder design targeted at high definition video applications is presented. The proposed design is compatible to decode H.264 Baseline Profile (BP), Main Profile (MP), and High Profile (HP) and AVS Juzhun Profile video sequences. It consists of hardware decoder, an efficient verification environment, and the associated firmware. It is optimized from both the viewpoints of system and component levels for high performance design consideration. In system level optimization, we simplify the control of the most complicated Macroblock Adaptive Frame/Field (MBAFF) coding tool, reduce the internal buffer size for storing the prediction data, and reduce the redundant latency in external memory accessing. In component level optimization, we improve the throughput rate in bit-stream decoding and integrate the processing units of H.264 and AVS together to reduce hardware cost. To ensure robust functionality, we adopt over 200 H.264 and AVS test sequences, including the conformance bit-streams provided by JVT for H.264, to verify the proposed design. Moreover, we adopt an ARM-based FPGA platform, called FIE-8100, to perform the FPGA verification of the proposed design. Through the proposed optimization techniques, the developed AVS/H.264 dual mode video decoder can achieve real-time HD1080 (1920x1088@30Hz) video decoding when it is operating at 150MHz.
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