| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 100 === With the increasing lack of energy resource, low power has become a tendency. Lowering supply voltage is the most straightforward and effective approach to reduce power consumption. However, under low voltage environment can make the performance of circuits worse. Therefore, how to achieve a target of low power consumption but still keeps the performance under low voltage. The TBLB is a technique with multiple supply voltages and can achieve the low power consumption but also enhance the circuit performance. But using TBLB technique has some restrictions. Therefore, this thesis provides the synthesis flow for TBLB, especially focus on the multiple supply voltage synthesis flow. Traditional synthesis flow can synthesis and analysis just with one power domain. Therefore, traditional synthesis flow is hard to meet the timing constraints of different power domain. This thesis provides the multiple supply voltage synthesis flow and can meet timing constraints of different power domain, and make the circuit to achieve the best power performance.
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