Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing

碩士 === 元智大學 === 資訊工程學系 === 97 === Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling...

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Main Authors: Chi-Wei Yu, 游濟維
Other Authors: Wang-Dauh Tseng
Format: Others
Language:en_US
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/67361267667834633583
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spelling ndltd-TW-097YZU053920512016-05-04T04:17:09Z http://ndltd.ncl.edu.tw/handle/67361267667834633583 Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing 決定式內嵌式自我測試架構下藉由多重線性回饋移位暫存器達到低功率測試 Chi-Wei Yu 游濟維 碩士 元智大學 資訊工程學系 97 Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling (MTF) on the test cubes. The technique of Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform is applied to pre-process the test data to help improve the compression effect. A BIST-based scheme using multiple LFSRs is then constructed to compress test data and generate the target test set. Experimental results show, this method can reduce the shift-in power significantly and also has good compression effect for larger ISCAS’89 benchmark circuits. Wang-Dauh Tseng 曾王道 2009 學位論文 ; thesis 19 en_US
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description 碩士 === 元智大學 === 資訊工程學系 === 97 === Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling (MTF) on the test cubes. The technique of Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform is applied to pre-process the test data to help improve the compression effect. A BIST-based scheme using multiple LFSRs is then constructed to compress test data and generate the target test set. Experimental results show, this method can reduce the shift-in power significantly and also has good compression effect for larger ISCAS’89 benchmark circuits.
author2 Wang-Dauh Tseng
author_facet Wang-Dauh Tseng
Chi-Wei Yu
游濟維
author Chi-Wei Yu
游濟維
spellingShingle Chi-Wei Yu
游濟維
Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
author_sort Chi-Wei Yu
title Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
title_short Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
title_full Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
title_fullStr Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
title_full_unstemmed Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
title_sort deterministic built-in self-test using multiple linearfeedback shift registers for low-power scan testing
publishDate 2009
url http://ndltd.ncl.edu.tw/handle/67361267667834633583
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