Deterministic Built-in Self-Test Using Multiple LinearFeedback Shift Registers for Low-Power Scan Testing
碩士 === 元智大學 === 資訊工程學系 === 97 === Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling...
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| Format: | Others |
| Language: | en_US |
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2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67361267667834633583 |
| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 97 === Large test data volume and excessive testing power are two strict challenges for today’s VLSI testing. This thesis presents a BIST-based method for reducing testing power. A low power test set is first determined through the application of minimum transition filling (MTF) on the test cubes. The technique of Neighboring Bit-wise Exclusive-OR (NB-XOR) Transform is applied to pre-process the test data to help improve the compression effect. A BIST-based scheme using multiple LFSRs is then constructed to compress test data and generate the target test set. Experimental results show, this method can reduce the shift-in power significantly and also has good compression effect for larger ISCAS’89 benchmark circuits.
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