| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 97 === Post-routing redundant via insertion (RVI) is an effective approach to forming double vias in a chip and effective algorithms have been invented for it. However, implementations of these algorithms often ignore some practical issues and hence constantly report exceedingly high RVI rates that are not achievable when these practical issues are considered. In this thesis, we implement a post-routing RVI algorithm that takes into account interconnect contexts during RVI. We especially focus on forming redundant vias at pin ports normally situated at metal layer 1. We also carry out reliability-driven RVI to increase RVI rates on timing critical paths. Our implementation has been ported to a commercial design flow and tested on benchmark circuits synthesized with a commercial standard cell library. Experimental results show that our context-aware RVI on average raises via1 (vias between metal layer 1 and 2) insertion rate from 37.4% to 72.1% and total insertion rate from 72.5% to 85.8%. On average, it increases RVI rate of critical paths by 3.6%. Besides, with redundant pin-area minimization, our approach reduces metal 1 and metal 2 area used for RVI at pins by 3%.
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