A Study on Depth-driven Quadrant Dispatching Placement
碩士 === 元智大學 === 資訊工程學系 === 97 === With the advance of semiconductor processing technology, wire delay dominates cell delay. Besides, the number of cells as well as the design complexity grows up rapidly in modern VLSI design. Hence, both the wirelength and timing problems must be carefully considere...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85439562701736939947 |