FPGA Design to an Variable Optical Attenuator Control Circuit

碩士 === 雲林科技大學 === 通訊工程研究所碩士班 === 97 === The dissertation uses the FPGA (Field Programmable Gate Array) to replace the 8051 (single-chip microprocessor) in the VOA (Variable Optical Attenuator) applications. In the whole system, the analog circuit includes the O/E (optical to electro) conversion, the...

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Main Authors: Shu-wen Pan, 盤舒文
Other Authors: Wan-De Weng
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/19448246104460776276
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spelling ndltd-TW-097YUNT56500052015-10-13T15:43:09Z http://ndltd.ncl.edu.tw/handle/19448246104460776276 FPGA Design to an Variable Optical Attenuator Control Circuit 以FPGA設計可調變光衰減器之控制電路 Shu-wen Pan 盤舒文 碩士 雲林科技大學 通訊工程研究所碩士班 97 The dissertation uses the FPGA (Field Programmable Gate Array) to replace the 8051 (single-chip microprocessor) in the VOA (Variable Optical Attenuator) applications. In the whole system, the analog circuit includes the O/E (optical to electro) conversion, the ADC (Analog to Digital Converter), the DAC (Digital to Analog Converter), the VOA driver, and rectifier circuits, and the digital circuits are designed on FPGA development board: the Max II Starter Kit and use the ALTERA Quartus Ⅱ 7.0 software to design, simulation, and burn. The digital circuits is divided into the input/compare circuit, the fine tune circuit, the default output value select circuit, the output buffer circuit, and the system clock generator circuit. In the system, the sampling rate is 512 kHz. When only use the fine tune circuit, the attenuation rates are changed from 3 dB to 10 dB and from 10 dB to 3 dB the transition times are 2.25 ms and 2.4 ms, respectively. When the default output value select circuit is used, the attenuation rates are changed from 3 dB to 10 dB and from 10 dB to 3 dB the transition times are 0.65 ms and 0.95 ms, respectively. The default output value select circuit can effectively reduce the transition times. When the default output value select circuit is used, too, the attenuation rates are changed from 0 dB to 19.87 dB(attenuation rate is 97)and 19.87 dB and 0 dB, the transition times are 0.5 ms and 0.76 ms, respectively, when un-use and use the default output value select circuit, respectively. The transition times are similar to the attenuation rates are changed from 3 dB to 10 dB and from 10 dB to 3 dB. Therefore, the transition times are independent on the changing of the attenuation rates when use the default output value select circuit. Wan-De Weng Yeong-Her Chen 翁萬德 陳永和 2009 學位論文 ; thesis 60 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 雲林科技大學 === 通訊工程研究所碩士班 === 97 === The dissertation uses the FPGA (Field Programmable Gate Array) to replace the 8051 (single-chip microprocessor) in the VOA (Variable Optical Attenuator) applications. In the whole system, the analog circuit includes the O/E (optical to electro) conversion, the ADC (Analog to Digital Converter), the DAC (Digital to Analog Converter), the VOA driver, and rectifier circuits, and the digital circuits are designed on FPGA development board: the Max II Starter Kit and use the ALTERA Quartus Ⅱ 7.0 software to design, simulation, and burn. The digital circuits is divided into the input/compare circuit, the fine tune circuit, the default output value select circuit, the output buffer circuit, and the system clock generator circuit. In the system, the sampling rate is 512 kHz. When only use the fine tune circuit, the attenuation rates are changed from 3 dB to 10 dB and from 10 dB to 3 dB the transition times are 2.25 ms and 2.4 ms, respectively. When the default output value select circuit is used, the attenuation rates are changed from 3 dB to 10 dB and from 10 dB to 3 dB the transition times are 0.65 ms and 0.95 ms, respectively. The default output value select circuit can effectively reduce the transition times. When the default output value select circuit is used, too, the attenuation rates are changed from 0 dB to 19.87 dB(attenuation rate is 97)and 19.87 dB and 0 dB, the transition times are 0.5 ms and 0.76 ms, respectively, when un-use and use the default output value select circuit, respectively. The transition times are similar to the attenuation rates are changed from 3 dB to 10 dB and from 10 dB to 3 dB. Therefore, the transition times are independent on the changing of the attenuation rates when use the default output value select circuit.
author2 Wan-De Weng
author_facet Wan-De Weng
Shu-wen Pan
盤舒文
author Shu-wen Pan
盤舒文
spellingShingle Shu-wen Pan
盤舒文
FPGA Design to an Variable Optical Attenuator Control Circuit
author_sort Shu-wen Pan
title FPGA Design to an Variable Optical Attenuator Control Circuit
title_short FPGA Design to an Variable Optical Attenuator Control Circuit
title_full FPGA Design to an Variable Optical Attenuator Control Circuit
title_fullStr FPGA Design to an Variable Optical Attenuator Control Circuit
title_full_unstemmed FPGA Design to an Variable Optical Attenuator Control Circuit
title_sort fpga design to an variable optical attenuator control circuit
publishDate 2009
url http://ndltd.ncl.edu.tw/handle/19448246104460776276
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