A Low Density Parity Check Decoder Using New Independent Column Operation Skill

• Main Authors: Ya-Ting Chan, 詹雅婷
• Other Authors: Po-Hui Yang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/48443290580986860899

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 97 === In this thesis, we adopt Log-Domain Sum-Product Algorithm (Log-SPA) to implement a modified low-density parity check code decoder in its check node part. From the prior art studies, we found that the look-up table is the most commonly use circuit being implemented in a traditional check-node hardware, and the main goal of this thesis is to propose a low hardware cost LDPC decoder, therefore we start from the traditional look-up table. Then, we propose a new independent column-wise operation skill to reduce the adder operations. It uses simply the concept of priority encoder which establishes a new binary weighting look-up table, so that a new simplified adder can be used for independent column-wise operation. The exact downing to valuable node value can be obtained by a recovery look-up table. The proposed new decoder is realized in the fully parallel architecture under the IEEE 802.16e standard that the matrix size is (1248, 624) and the code rate is 1/2. When compare with the traditional LDPC decoder hardware, the total chip area reduces about 28%, and the operational speed can reach up to 111MHz with only 0.1dB BER difference under TSMC 0.18um cell-based technology. In the same condition, the proposed decoder can save about 22% hardware by using UMC 90nm cell-based technology. The implemented test chip equipped with real-time on-chip self-test circuits which have an Additional White Gaussian Noise generator, and associated mode control circuits. The implemented chip, in TSMC 0.18um cell-base technology, shows that our new LDPC decoder architecture has low-cost and high-performance characteristics.