| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 97 === This thesis presents the research and implement on low noise amplifier for Ultra wide band receiver front-end。The chips are fabricated by TSMC 0.18um CMOS process. The efficiency of the circuit was demonstrated by measurement.
In first chip, adopt the principle of common gate amplifier with gm-boosting technique to design a low noise amplifier for high gain requirement. Measurement results is shown that maximum gain of 6.8dB, noise figure (NF) of 6.4dB, S11 of -11dB, and S22 of about -7.5dB with the DC power dissipation 23mW under 1.8V power supply. The IIP3 is +18dBm at 3GHz.
In second chip, we utilize the principle of current-reused and common gate configuration to design a low noise amplifier for low power application. The minimum noise figure is 4.6 dB and maximum gain is 12dB from 3.1 to 10.6 GHz while drawing 9.75mW from a 1.5V supply voltage. The input and output return loss are both better than -8dB, isolation better than -42dB, respectively. The IIP3 is -6.25dBm at 8GHz.
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