| Summary: | 碩士 === 國立臺北科技大學 === 電資碩士班 === 97 === Due to the portable computer, communication, and consuming electronic grew up extensively. In the application of the display and wireless communication ,as to the low power, and high speed, that the interface circuit of analog to digit converter has indispensable demands. The pipelined analog to digital converter is a better choice at present which has high speed conversion ratio and high resolution for the analog to digital converter.
The main structure used the 9 stages pipelined ADC. In this thesis the 10 bits pipelined ADC is composed of the first 8 stages which each stage 1.5 bit and the last stage that has 2 bit. In order to get low power, high speed, and high resolution , each stage used the dual channel 1.5bit Flash ADC. Because of the 1.5bit flash ADC have high-speed operation advantage and the dual channel structure can decrease the power consumption and reduce the noise when it work in positive and negative duty cycle respectively. We descript the basic principle of pipelined analog to digital converter and realize from designing to the circuit. We adopt the TSMC 0.18 μm CMOS technology to simulation the circuit of system and implement it. the core area is about 0.6 1.47 mm2, and the power consumption is about 21.6mW. If the bandwidth of the input signal is 44.1 kHz sine wave, we obtain the 41.5 dB peak signal to noise and distortion ratio, and simulation results ENOB=6.6 bits.
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