Twisted-Overlap Differential-Pairs Design with High Reliability and Optimal Layout Space

碩士 === 國立臺北科技大學 === 電資碩士班 === 97 === Nowadays, the Differential-Pairs design has owned the advantages of high immunity noise capability, high transmission bandwidth, and less layout space. Therefore, in this study, we propose a novel layout approach for Differential-Pairs, called Twisted-Overlap Dif...

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Bibliographic Details
Main Authors: Chun-Yen Lu, 劉俊彥
Other Authors: Wen-Tzeng Huang
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/t64kd8
Description
Summary:碩士 === 國立臺北科技大學 === 電資碩士班 === 97 === Nowadays, the Differential-Pairs design has owned the advantages of high immunity noise capability, high transmission bandwidth, and less layout space. Therefore, in this study, we propose a novel layout approach for Differential-Pairs, called Twisted-Overlap Differential-Pairs (TODP), to reduce the layout space without lowering the transmission bandwidth. Compared with the Twisted Differential-Pairs (TDP) in the literal, our approach is to employ the different layers and then to overlap the same PCB vertical space for reducing the layout routing space. Hence, our proposed method can get the more space for other components and the width of the layout space. Compared with the other two layout methods, our proposed approach can save 17% layout space than that of the others under the 16 Differential-Pairs in the experiments. Moreover, a factor is defined as the amount of the noise within one unit layout area, called evaluation factor = (noise factor / one unit layout), where noise factor is the amount of the eye high, jitter, and eye height. Hence, a less factor is more performance. From our experiment results to verify our method, the evaluation factors of the tradition Differential-Pairs, TDP, and our approach designs are 4.00, 4.29, and 3.10, respectively. Therefore, our method is the best method among them. From our experiment results, our approach can be implemented in the PCB layout strategy such that it can get the more layout space for components under the good signal integration condition.