A Study on the Hot-Carrier Reliability of 200V SOI PLDMOS
碩士 === 亞洲大學 === 資訊工程學系碩士班 === 97 === The reliability of the high voltage P-LDMOS is examined extensively by moving the impact ionization area and varying the surface electric field in the drift region. Breakdown walkout in high-voltage P-LDMOS devices on a thin SOI layer is demonstrated closely rela...
Main Authors: | Hui-Ting Yang, 楊惠婷 |
---|---|
Other Authors: | Shao-Ming Yang |
Format: | Others |
Language: | zh-TW |
Published: |
2009
|
Online Access: | http://ndltd.ncl.edu.tw/handle/17003352917403750503 |
Similar Items
-
Study of HCI Reliability for PLDMOS
by: Deivasigamani Ravi, et al.
Published: (2018-01-01) -
A Study of ESD-Reliability Strengthening by Layout Structure Modulations in HV 32V/60V pLDMOS Devices
by: CHIU, YI-HAO, et al.
Published: (2018) -
An Innovated UHV PLDMOS device with improved HTRB Performance
by: Monika Bharti, et al.
Published: (2019) -
Study on Characteristics of PLDMOS Transistors with LOCOS and Tapered Oxide Structures
by: Tumur-Ochir Demberel, et al.
Published: (2012) -
Reliability test of high voltage SOI device under Hot carrier injection stress
by: Luvsanperenlei Magsarsuren, et al.
Published: (2012)