A DPLA Compiler with Various Schemes

• Main Authors: Yu-Hun Pan, 潘裕諢
• Other Authors: Tzyy-Kuen Tien
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/25560883860044886786

碩士 === 南台科技大學 === 電子工程系 === 97 === Nowadays due to Programmable Logic Array (PLA) possesses the advantages of structure regularity and data access time predictability, it is highly suitable to design an automated logic circuit. Dynamic Programmable Logic Array (DPLA), moreover, has the benefits of high speed performance[1][2][3] and low power consumption[4][5] while maintaining the original advantages of PLA. Therefore, many developed DPLA structures have been widely adopted for implementing control logic circuit in high-end processors[6]. Even so, a single DPLA structure cannot be applied to all circuits. Besides, it takes further working hours and human resource costs to design a circuit by fully custom methodology. For these reasons, this paper aims at DPLA to design a compiler with various schemes. The compiler is able to generate a low power, high speed DPLA layout or a low leakage power one. When we implementing a circuit of DPLA, the compiler will select the scheme appropriately according to the design constrains input by users, and chooses the proper dimension of input/output buffers, inter-buffers, and clock buffers established in advance to synthesis a layout. Then generating a netlist file to facilitate the subsequent verification work (e.g. LVS, PEX, etc) automatically.