Implementation of a new Architecture SRAM and Low Power Application

• Main Authors: Chou-Mine Laio, 廖秋明
• Other Authors: Po-Mine Lee
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/03656620585337890239

碩士 === 南台科技大學 === 電子工程系 === 97 === With the development of semiconductor, the demand of low power as well as low cost is the primary claim in all electronic products. Nowadays, more and more transistors are integrated into the core of modern chips which requires more demand in memory circuits, too. Thus, we choose memory as research target. Device sizes shrinks in deep-submicron process causes some problems like noise and parasite effects. All those effects consumes more and more power which can not be neglected at all. In addition, static power consumption is also more and more obvious. Hence, we try to propose new SRAM (Static Random Access Memory) to overcome power consumption problems caused by leakage current. The result can be more power efficient. Besides, it will also reduce the problems caused in deep-submicron process. According to our comparison, the proposed design posesses the advantages in dynamic power consumption, static power consumption and operating speed. Besides the mentioned problems, the circuit is causing extra power consumption in charging/discharging operation. In order to inhibit unwanted power consumption of the bit lines, we add selectable charge bit line design to reduce power consumption. We also add GLSENAD address sense circuit in address sense circuit. In short, we provide a new architecture of SRAM design. The proposed design is realized by TSMC (Taiwan Semiconductor Manufacturing Company) 0.18 um CMOS process. The simulation is done by HSpice.