A High Efficiency Dual-Mode Switching Boost Regulator

• Main Authors: Wei-Jian,Jhang, 章偉健
• Other Authors: Mei-Ling,Ye
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/87239862955904884345

碩士 === 聖約翰科技大學 === 電子工程系碩士班 === 97 === This thesis implements a switching boost regulator for applications in portable products, which combines pulse width modulation mode with pulse frequency modulation mode on a chip successfully. It has the advantages of high conversion efficiency, low quiescent current, and low output ripple. In order to have higher conversion efficiency in any condition of loads, the regulator uses dual conversion modes in the system. By choosing suitable mode for different loads, it can increase the conversion efficiency of the whole system effectively. Avoiding the regulator from damaging devices with momentarily excess large current, we adopt the concept of soft start when the system is started up. This design can prevent the blocks of circuit from being damaged during starting up the regulator. In order to increase the conversion efficiency of the regulator, in partial blocks of circuit we add choose of disable and enable, and concept of reset. Recovering the circuit to initial state when disable signal is turned on, it can avoid problems which may occur during re-enable of circuits. This thesis designs and implements a high conversion efficiency dual-mode switching boost regulator by using TSMC 2P4M 0.35um CMOS process. The simulation results show that an output voltage is 5V±0.2V with an input voltage range from 2.7V~3.3V, chip size is 2140um×2093um, the output ripple is 16mV in PWM mode and 30mV in PFM mode, and the maximum conversion efficiency of the regulator can be 94.9%.