900 MHz 8-bit passive CMOS RFID Tag Design
碩士 === 國立臺灣科技大學 === 電機工程系 === 97 === This thesis presents a 900MHz 8-bit passive CMOS RFID Tag with 40-stage charge pumps. There is no oscillator in the proposed tag to save power such that the read distance is increased. The tag is fabricated using the TSMC 0.18 μm CMOS process. The measured minimu...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98605949660315298677 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 97 === This thesis presents a 900MHz 8-bit passive CMOS RFID Tag with 40-stage charge pumps. There is no oscillator in the proposed tag to save power such that the read distance is increased. The tag is fabricated using the TSMC 0.18 μm CMOS process. The measured minimum input power is -16.7dBm, the supply voltage is 0.7V to 1.6V, and the charge pump’s maximum power efficiency is 33% at input power equal to －21 dBm.
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