Network Accelerator Engine

• Main Authors: Shane-Feng Yu, 游勝帆
• Other Authors: Sheng-De Wang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/74056378186747183245

碩士 === 國立臺灣大學 === 電機工程學研究所 === 97 === Network Accelerator Engine Abstract The wired speed of the local area network has been increased from 10/100 Mbps to 1G/10 Gbps recently and deep packet inspections are required in real-time by firewall machines to secure the Internet services. The processing of network packets has become the system’s major bottleneck. Network accelerator engines can offload the computing need of CPU with a specific design circuit. In this thesis, we design and implement a Network Accelerator Engine to accelerate the processing speed of TCP/IP protocol stack in an embedded system. The proposed offload engine is consisted of four modules, namely, Datagram Receiver Module, Network Accelerator Module,Checksum Module, and Access Control List Module. In the proposed offload engine, we directly retrieve packets from the media access controller (MAC) and parse them for IP headers and payload without using any processor bus and interrupt. In a result, the packet processing speed does not depend on any software or CPU architecture.In current implementation in an Altera Cyclone II platform, we can achieve the data throughput of 100Mbps, which is the wired speed of the system’s MAC.