| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 97 === Nowadays, mobile devices are incorporated with more and more communication standards. Currently, several ASICs are combined to support the multi-mode operation in a mobile device. However, this is neither an efficient nor a flexible solution when more radio interfaces are added. Software-Defined Radio tends to use programmable processors to reconfigure on the fly and switch from one radio interface to another. With future communication standards having computation complexity up to 100s and even 1000s of GOPS, current DSP processors with VLIW architecture will not be able to meet the real-time requirements. This requires the research for a more suitable architecture for communication related algorithms. Coarse-grained reconfigurable architectures have gain attention in the application of SDR. This class of processors embeds a large amount of processing units arranged in a 1D/2D array. The granularity of processing elements spreads over a wide range, from an ALU to a simple RISC processor.
They tend to provide t of processing power by incorporating many functional units. Inspired by reconfigurable architectures, we propose architecture consists of a wide 1D ALU array, which tends to compute each operation related to the input data simultaneous. This kind of computation is suitable for FIR filtering, matrix-vector multiplications and other digital communication algorithms. A global data bus is used to broadcast inputs to all PEs and a reconfigurable data exchange bus is utilized to pass data between ALUs, which tends to compute each operation related to the input data simultaneous. This kind of computation is suitable for FIR filtering, matrix-vector multiplications and other digital communication algorithms. A global data bus is used to broadcast inputs to all PEs and a reconfigurable data exchange bus is utilized to pass data between ALUs.
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