| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === Pipelined analog-to-digital converters (ADCs) have been widely utilized in mid-resolution, high-speed applications. In this thesis, a background digital calibration technique based on the split ADC is proposed to correct linear errors in a pipelined ADC, which allows the use of simple-structured low-gain opamps in conversion stages. Raw output codes of the designed ADC exhibit a SNDR and a SFDR of merely 35.3 dB and 37.3 dBFS, respectively. As the associated linear errors are adaptively removed by the proposed calibration technique, the SNDR and the SFDR are improved to the level of 55.2 dB and 67 dBFS. Furthermore, the proposed calibration system converges in less than 10ms at 50MS/s, showing a significant improvement over previous works.
Fabricated in the 0.35um CMOS technology, the core this split pipelined ADC occupies 1.64mm2. The introducing of opamp-sharing technique reduces the core power consumption to 45mW from a 3V supply voltage at 50MS/s. At the end of this thesis, a nonlinear calibration technique combining the linear approximation and the split concept is developed to enhance the resolution for pipelined ADCs realized with open-loop amplifiers.
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