VLSI Placement Considering Routability, Performance, and Reliability

• Main Authors: Zhe-Wei Jiang, 江哲維
• Other Authors: Yao-Wen Chang
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/00105397007703589555

博士 === 國立臺灣大學 === 電子工程學研究所 === 97 === Placement is a major step in physical design that has been studied for several decades. Although it is a classical problem, modern design challenges have reshaped this problem. As a result, it is usually desired to consider various objectives during the placement process. For example, most existing placement algorithms focus on wirelength optimization and ignore the real design issues, such as routability and performance. Furthermore, to reduce the re-spin cost induced by post-silicon debugging and solve the reliability issues for the manufacturing process, several types of extra components (e.g., spare cells and antenna diodes) must be inserted into whitespace after the placement is done. If we can consider these components during the placement process, it will then reduce the difficulties of finding available positions for these components. In this dissertation, we propose several novel algorithms for VLSI placement generation to consider routability, performance, and reliability. This dissertation starts from a routability-driven analytical placement with a new direction/technique, called net overlapping removal, to solve the essential routability issue. Then the timing-driven analytical placement, which models the exact timing objective into the analytical formulation, is proposed to optimize the circuit timing during the placement optimization process. Despite of the routability and timing issues, the manufacturing process may also introduce additional design difficulties. Therefore, to fix the design failure caused by the manufacturing process, we propose a spare-cell-aware analytical placement and a multilevel spare cell insertion to generate a better distribution of spare cells. To reduce the reliability degradation caused by the antenna effect during manufacturing, we propose a diode-aware analytical placement to reduce the difficulties faced by the later stage for diode insertion. We further propose a simultaneous diode/jumper insertion algorithm to solve the antenna fixing problem.