Lithography Friendly Multilevel Analytical Placement

• Main Authors: Wen-Chi Chao, 趙文綺
• Other Authors: Yao-Wen Chang
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/82062896411092594825

碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === Due to the sub-wavelength lithography, manufacturing requires intensive use of Resolution-Enhancement Techniques (RETs), among which Optical Proximity Cor- rection (OPC) is the most popular technique in industry, to improve printability. Moreover, physical design for manufacturability becomes the major trend in the design flow to assist the success of manufacturing. In this thesis, we propose the first lithography friendly multilevel analyt- ical placement considering OPC. We first generate a cell-to-cell lithography cost model based on post-OPC lithography simulation, and then use this model to guide our placement. Based on the multilevel analytical placement framework, we use a probability-based cost estimation model for the clustering process, and a ratio- based cost estimation model for the spreading process, to estimate lithography cost. The clustering and spreading processes are adjusted by our cost estimation models. With the information provided by our model, our global placement is able to gen- erate a low lithography cost result for the next stage. Then legalization aligns cells to nearby rows considering lithography cost. Finally, detailed placement simultane- ously optimizes lithography cost and wirelength. We test our approach on ISCAS benchmark circuits [2] and ISPD04 IBM benchmark circuits [1]. Based on the experimental results, our lithography friendly detailed placement alone can already achieve 15.06% and 36.86% lithography cost reduction. The results are 13.94% and 34.01% better on printability than the pre- viously proposed detailed placement algorithm－Multiple-Row Optimization Algo- rithm [12], which is the most effective algorithm in the literature. To examine the effectiveness of our approach, we apply different placement flows and compare the results with the un-lithography-aware wirelength-driven NTUplace3 [6]. The effec- tiveness of each stage and the positive impacts between different stages are observed from the results. By applying the complete flow (which has the highest quality on printability) of our lithography friendly placement, we can achieves 20.86% and 50.94% lithography cost reduction on ISCAS benchmark circuits [2] and ISPD04 IBM benchmark circuits [1], respectively, comparing with wirelength-driven NTU- place3, with only less than 3% wirelength overhead. The results show that our approach can effectively achieve significant improvements on printability, which has the best results among all the related works, without notable wirelength quality decrease.