| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === In designing an integrated circuit (IC), many design decisions are known only to its designers. These decisions can be exploited for inexpensive and secure design protection. Under this principle, we propose an active IC metering scheme to protect intellectual properties (IPs) against unauthorized use and reverse engineering. It may benefit both IP vendors and IC design houses.
Rather than inserting an encryption/decryption or obfuscation circuit into a design as suggested by prior work, we exploit existing components for secure protection. Our methodology admits minimal perturbation to the design flow, such as verification and testing. The feasibility of our protection relies on the existence of a universally reachable state (URS) of an induced circuit of the protected design. Our method is complete and suitable for all synchronous sequential designs. By embedding a hardware component called an image restrictor, a design which does not have a URS can be made protectable. Experiments show that, without introducing image restrictors, still all of the ISCAS and ITC benchmark circuits are protectable under our method with negligible overheads.
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