Novel Algorithm and VLSI Design of Correlation Architecture for GNSS Signal Acquisition

• Main Authors: Chia-Ming Chang, 張家銘
• Other Authors: 曹恆偉
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/69077130188279470373

碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === Correlation architectures are widely used in various communication systems’ receiver, especially for the spread spectrum system, and they play an indispensable role in signal acquisition. With the mature development of GNSS (Global Navigation Satellite Systems), such as the GPS of U.S., the Galileo system of European Union, as well as the GLONASS of Russian, and even Japan, China are developing their own commercial satellites system to offer wide range of services. Therefore, in order to provide faster commercial navigation ability, the TTFF (Time To First Fix) of signal acquisition becomes one important indicator to gauge the performance of various kinds of receivers. Among these receivers, the design of correlator has the most important influence on TTFF. From different code phase searching methods of signal acquisition, and different types of correlators, we can conclude three common signal acquisition receiver architectures: sequential-input correlator with parallel code phases search, matched-filter with serial code phase search and fast Fourier transform method. Among these methods, the hardware complexity and the cost are too high for matched-filter with parallel code phases search although its TTFF is shortest. Therefore, only few people adopt this method in practical design. For this reason, this thesis proposed one efficient algorithm design flow for navigation satellites systems. By using subexpression elimination method, we designed an efficient hardware architecture which has advantages of area reduction of die size, enhancement of hardware utilization, reduction of TTFF, and low power consumption, etc. In addition, for software receiver application, the flexible design of the algorithm can tremendously reduce the required number of addition and multiplication. In hardware implementation, the proposed correlator architecture is implemented in 0.18 um CMOS process. The proposed design can provide searching 32 GPS L1 C/A code signals simultaneously and the implemented die size is about 1.86mm × 1.86mm.