Study of Twin Poly-Si Thin Film Transistors nonvolatile memory with Tri-Gate Nanowires Structure

• Main Authors: Po-Wen Su, 蘇博文
• Other Authors: Yung-Chun Wu
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/65672991313452525714

碩士 === 國立清華大學 === 工程與系統科學系 === 97 === In recent years, low-temperature polycrystalline silicon thin-film transistors (poly-Si TFTs) have drawn much attention because of their widely applications on active matrix liquid crystal displays (AMLCDs) , and organic light-emitting diodes (OLEDs) . Furthermore, low-temperature poly-Si TFTs will help to carry out the three-dimensional integrated circuits (3D-ICs) or multilayer Si ICs for system-on-chip (SoC) applications and fully functional system-on-panels (SoPs) in the future.It means that periphery circuits, key devices, and driving circuits all integrated on glass substrate. And nonvolatile memory (NVM) have been manufactured over thirty years, it has been becoming more and more important in the semiconductor industry because of their widely application for data storage. Based on previous experimental results, the NWs poly-Si TFT has the superior electrical characteristics due to the tri-gate structure and additional corner current induced by corner effect. In first part of this thesis proposed the twin poly-Si thin film transistor nonvolatile memory with tri-gate nanowires (NWs) structure. The experimental results show that the NWs device has superior electrical characteristic than the single channel (SC) one. Since the crowding of the gate fringing field at the narrow channel surface of NWs causes the large electrical field, the NWs devices with have the better gate control ability. The high electrical field verified enhancement of P/E efficiency in twin poly-Si TFT NVM due to the corner effect. Besides, this thesis demonstrated the different gate length and different coupling ration devices to discuss the coupling ration effect and floating gate length effect. The presence of polysilicon grain boundary defects in the channel region of TFTs drastically affects the electrical characteristics. Reducing the number of polysilicon grain boundary defects will improve the performance of poly-Si TFTs. NH3 plasma passivation has been reported to reduce the number of trap–states in poly-Si grain boundaries, yielding high-performance poly-Si TFTs. Thus, in the second part of this thesis, the twin poly-Si TFT NVM with NH3 plasma passivation is demonstrated. NH3 plasma passivation present better electrical characteristic, increase memory window, improve retention and decrease operation voltage.