Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis
博士 === 國立清華大學 === 電機工程學系 === 97 === Scan test has been an indispensable test methodology for guaranteeing test quality in industry. However, as the designs become larger and larger, the cost of scan test has been skyrocketing as the test data volume grows prohibitively high and thus increasing the t...
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ndltd-TW-097NTHU54421002015-11-13T04:08:49Z http://ndltd.ncl.edu.tw/handle/23127442066816387353 Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis 支援低功率測試與易診斷特性的掃瞄測試架構 Tzeng, Chao-Wen 曾昭文 博士 國立清華大學 電機工程學系 97 Scan test has been an indispensable test methodology for guaranteeing test quality in industry. However, as the designs become larger and larger, the cost of scan test has been skyrocketing as the test data volume grows prohibitively high and thus increasing the test time proportionally. At the same time, excessive test power consumption is causing yield loss during the scan test. Moreover, diagnosis quality has degraded significantly when test compression is in use. In addition, it is often desirable to port the scan test methodology to a low cost indirect-access test environment. Facing the above challenges, this thesis will focus on the development of comprehensive scan architecture so that it can meet the above stringent requirements, i.e., low-power test compression with good diagnostic capability while being portable to an indirect-access test environment. For test data volume reduction, we propose multicasting-based scan architecture named Universal Multicasting Scan (UMC-Scan). As compared to the most advanced multicasting-based architectures, the experimental results will demonstrate that the proposed architecture can significantly improve the test compression ratio. For reducing test power consumption, a post pattern generation flow named Quick-and-Cool X-fill (QC-Fill). The proposed X-fill method can properly utilize the don’t-care bits in the test patterns to simultaneously reduce the test power, while retaining high test compression ratio. For porting scan test to a wireless test platform, called HOY test platform, indirect-access scan architecture will be introduced to improve the test efficiency when scan test is adopted in an indirect-access test environment. Finally, for compensating the loss of diagnostic resolution resulting from output compaction, we propose an output masking scheme. The experimental results demonstrate the proposed scheme can recover the diagnostic resolution loss induced by an output compactor almost completely without sacrificing the compaction ratio. Huang, Shi-Yu 黃錫瑜 2009 學位論文 ; thesis 105 en_US |
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博士 === 國立清華大學 === 電機工程學系 === 97 === Scan test has been an indispensable test methodology for guaranteeing test quality in industry. However, as the designs become larger and larger, the cost of scan test has been skyrocketing as the test data volume grows prohibitively high and thus increasing the test time proportionally. At the same time, excessive test power consumption is causing yield loss during the scan test. Moreover, diagnosis quality has degraded significantly when test compression is in use. In addition, it is often desirable to port the scan test methodology to a low cost indirect-access test environment.
Facing the above challenges, this thesis will focus on the development of comprehensive scan architecture so that it can meet the above stringent requirements, i.e., low-power test compression with good diagnostic capability while being portable to an indirect-access test environment. For test data volume reduction, we propose multicasting-based scan architecture named Universal Multicasting Scan (UMC-Scan). As compared to the most advanced multicasting-based architectures, the experimental results will demonstrate that the proposed architecture can significantly improve the test compression ratio. For reducing test power consumption, a post pattern generation flow named Quick-and-Cool X-fill (QC-Fill). The proposed X-fill method can properly utilize the don’t-care bits in the test patterns to simultaneously reduce the test power, while retaining high test compression ratio. For porting scan test to a wireless test platform, called HOY test platform, indirect-access scan architecture will be introduced to improve the test efficiency when scan test is adopted in an indirect-access test environment. Finally, for compensating the loss of diagnostic resolution resulting from output compaction, we propose an output masking scheme. The experimental results demonstrate the proposed scheme can recover the diagnostic resolution loss induced by an output compactor almost completely without sacrificing the compaction ratio.
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Huang, Shi-Yu |
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Huang, Shi-Yu Tzeng, Chao-Wen 曾昭文 |
author |
Tzeng, Chao-Wen 曾昭文 |
spellingShingle |
Tzeng, Chao-Wen 曾昭文 Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis |
author_sort |
Tzeng, Chao-Wen |
title |
Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis |
title_short |
Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis |
title_full |
Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis |
title_fullStr |
Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis |
title_full_unstemmed |
Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis |
title_sort |
scan architecture supporting low power test compression and easy diagnosis |
publishDate |
2009 |
url |
http://ndltd.ncl.edu.tw/handle/23127442066816387353 |
work_keys_str_mv |
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