Improving Testing and Diagnosis Efficiency of Regular Memory Arrays

• Main Authors: Wu, Tsung-Yu, 吳宗祐
• Other Authors: Wu, Cheng-Wen
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/25901583105928766445

碩士 === 國立清華大學 === 電機工程學系 === 97 === Embedded memory cores are widely used in the SOC, and the area percentage of embedded memory cores in the SOC is growing rapidly. Since the high density and capacity of embedded memory cells, the probability of faulty bits is high and the chip yield will be affected. Therefore, embedded memory testing, diagnosis and repair are required to improve the testability, yield and reliability. Built-in Self-Test is one of the most used design-for-test (DFT) circuit to test embedded memory. It provides accessibility, scalability, programmability, low area overhead and flexibility. The conventional BIST is attached to each memory core or shared by several cores; however, for the regular memory array with large core number, the conventional BIST methods become inefficient in terms of test time and area overhead. BRAINS is a BIST generator to generate the BIST design. It features parallel testing, hardware sharing, at-speed testing, diagnosis support and grouping/scheduling. However, in testing the multi-core array, the testing and diagnosis flow is not efficient that the total test time is directly proportional to the memory cores. In this work, we propose a BIST generator BRAINS\_A which is based on the BRAINS design that can generate BIST circuit to test the memory array efficiently. BRAINS\_A supports early stop in the test mode and automatic parallel diagnosis with data compression in the diagnosis mode. With these modified functions, the testing and diagnosis flow becomes simple and the overall test time can be reduced by 6 to 23 times with area overhead increased from 10\% to 17\% in the experiment of a 32-core memory array.