A multi-mode decoder architecture for RS-LDPC codes

• Main Authors: Wang, Kuan-Chieh, 王冠傑
• Other Authors: Ueng, Yeong-Luh
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/71053854055080951654

碩士 === 國立清華大學 === 電機工程學系 === 97 === For an efficient multi-mode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi cyclic, in this thesis, we re-veal that the structural properties inherent in its parity-check matrix can be adopted in the design of congurable permutators. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the throughput. To further increase the throughput, shuffled message-passing decoding is adopted to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance. Using a 90-nm CMOS process, multi-mode decoders that can achieve multi-Gbit/s throughput have been implemented.