| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 97 === For the 3rd Generation Partnership Project(3GPP) specification, the turbo code is applied
in the transmitted data because the data needs a better error correction capability.
With the increase of the utilization of the turbo decoder in the next generation system,
decoding speed for the MAP decoder has become more and more critical. Hence, the
target of this thesis is to design a high throughput MAP decoder for the turbo decoder.
We propose a radix-16 MAP algorithm to reduce the decoding cycle, and a modified
term method to improve the decoding performance. Then, we propose a separate-CS
architecture which can operate sixteen inputs simultaneously to reduce the latency of
the MAP decoder, and a cut-bank-jump-permute method for the interleaver memory
to solve the collision problem. Finally, we implement the proposed high-radix modified
log-MAP decoder. The throughput of the proposed decoder is 393Mb/s which is better
than some references. Moreover, the proposed decoder can combine the other techniques
even to increase the throughput in the same performance.
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