| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 97 === In designing power devices using conventional P/N junctions, the tradeoff between breakdown voltage (Bv) and on-state resistance (Ron) has always been a major concern. Many studies have proposed various structures to sustain high Bv level while reducing the Ron. However, it is generally believed that under the same Bv, there is a limit on how low Ron can be, which is called “Silicon-limit”.
By adapting the Super Junction (SJ) concept, highly doped SJ structure can effectively improve the Bv while reducing the Ron; hence break the Silicon-limit. Due to its superior characteristics, SJ has become the promising solution in high voltage power device applications. The fabrication of SJ devices faces the challenge of creating P/N pillars with matching impurity concentrations after thermal process.
This thesis introduced a novel Charge-Balance-Enhanced Super Junction MOSFET, CBE-SJ MOS; which helps to promote charge-balance in the super junctions. By TCAD simulation, the newly designed cell and termination structures of CBE-SJ MOS is proven to endure 600Volt reverse voltage with ultra low on-state resistance.
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