High Program Efficiency of P-Type Floating Gate in N-Channel Split-Gate Embedded Flash Memory

• Main Authors: Shih, Hung-Sheng, 施宏昇
• Other Authors: Lin, Chrong-Jung
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/59631914528415782831

碩士 === 國立清華大學 === 電子工程研究所 === 97 === Recently, the Split Gate Flash Memory has been widely discussed and employed in nonvolatile semiconductor memories. For the design of advanced Flash Memories, the performance and reliability are the major concern. In the past, the design of flash memories is mainly focused on the development of the novel cell structure, the source/drain engineering, the floating gate engineering, and the operation methods. In this thesis, we focus on the idea of floating gate engineering to improve the device characteristics, to propose for the first time a new design of P-type floating gate on N channel split gate flash memory. We change the floating gate doping from N-type to P-type with different P-type doping concentration. Based on the experimental results, the N-type floating-gate split gate flash cell has much better performance and reliability than the conventional n-type floating-gate one. In other words, the P-type floating-gate split gate flash cell has faster programming/erasing speed, larger operation window, and better endurance characteristics. Finally, a 2Mbits embedded Flash IP was been successfully implemented statistically compared. The new p-doped split gate structure provides a very promising solution for advanced embedded split-gate Flash memory beyond the 90nm node.