Design and Implementation of 40Gbps Ultra High Speed VOQ
碩士 === 國立清華大學 === 資訊工程學系 === 97 ===
Main Authors: | Tsai, Shih Min, 蔡世敏 |
---|---|
Other Authors: | Lee, Duan Shin |
Format: | Others |
Language: | zh-TW |
Published: |
2009
|
Online Access: | http://ndltd.ncl.edu.tw/handle/52008799720847641275 |
Similar Items
-
An FPGA Implementation of 40Gbps Ultra High Speed VOQs
by: Lee, Ta-I, et al.
Published: (2010) -
An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
by: Chu-Sheng Ku, et al.
Published: (2008) -
An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Dump Process, Segmentation and Reassembly
by: Chun-Yeh Chen, et al.
Published: (2008) -
The FPGA Implementation of a 40Gbps Ultra High Speed Queue – Data Switch Controller and DeQ Method
by: Chih-Hsien Lu, et al.
Published: (2008) -
Emulation of OQ Switches Using 3D-VOQ Switches
by: Hsuan-Kuei Cheng, et al.
Published: (2005)