Design of the Low-Density Parity-Check CODEC for Non-Volatile Memories

• Main Authors: Ho,Chi-Da, 何啟達
• Other Authors: Huang,Chih-Tsun
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/81646210630842251429

碩士 === 國立清華大學 === 資訊工程學系 === 97 === In this thesis, we evaluated the existing technologies of LDPC (low-density parity check) codes for the error correcting scheme of the non-volatile memories. With the consideration of the cost-effectiveness, the ¼-matrix approach has been adopted for the parity-check matrix. The system model was constructed to evaluate the performance and encoding/decoding behavior of our LDPC CODEC (Encoder/Decoder) with various code rates. After the analysis of coding performance, we used sum-product algorithm in logarithm domain as the decoding approach, and adopted the layered belief propagation algorithm. In addition, the decoding indexes are implemented with integer numbers to simplify the hardware. The overall LDPC CODEC is area efficient. The scalable architecture makes our CODEC suitable for a large variety of code rates. Parallel architecture can be easily implemented to speed up the throughput. In addition, the memory usage is dramatically reduced in our design without affecting the correcting performance. A design for the modern flash memory has been implemented to validate our LDPC CODEC. Our future works includes the study and design of the hybrid BCH and LDPC codes to further increase the effective code rate, also the searching of the more efficient LDPC codes, and the improvement of the encoding/decoding architecture, with the consideration of the future non-volatile memories and solid-state disks.