| Summary: | 碩士 === 國立屏東科技大學 === 工業管理系所 === 97 === This thesis investigates the bottleneck of TFT LCD product development activities, that is, reliability tests. The operations of reliability testing machines are seen as unrelated parallel machines. Genetic algorithms is used to constraints the proposed scheduling scheme, which is further divided into preemptive and non-preemptive methods, to solve the scheduling problems with constraints such as machine capacity, due dates, and test criteria. The goal is to minimize the make span. The results are compared to the results of the currently used dispatching rule, FCFS.
The test result indicates that in the case of small-sized TFT LCD panels, the non-preemptive scheduling results in a make-span 40% less than the current FCFS method. In the case of large size panels, the preemptive scheduling results in a make span 43.4% better than FCFS. By reducing the test make-span, of new products can be launched ahead of planned schedule. In this way, customer satisfaction, product demand and expectation could be fulfilled, thus ultimately uplift corporate's market share and competitiveness.
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