A Digital Controlled Multi-Phase Delay Locked Loop with Calibration Technique

A Digital Controlled Multi-Phase Delay Locked Loop with Calibration Technique

碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 97 === This thesis presents a digital-controlled delay line with digital to voltage converter (DVC) to achieve fast locking. In addition, the digital to voltage converter is applied in a digitally controlled Delay Locked Loop (DLL). The advantages of combining digi...

Full description

Bibliographic Details
Main Authors:	Tsung-Hsiang Lin, 林琮翔
Other Authors:	Pao-Lung Chen
Format:	Others
Language:	zh-TW
Published:	2009
Online Access:	http://ndltd.ncl.edu.tw/handle/21223633502549330752

Similar Items

Digital Multiplying Delay-Locked Loop Using Switched Biasing Technique and Digital Phase-Locked Loop with Bandwidth Calibration
by: Chi-Huan Chiang, et al.
Published: (2014)

Delay-Locked Loops with phase error calibration
by: Jian-Da Lin, et al.
Published: (2012)

Delay-Locked Loops with phase error calibration
by: Chih Wei Huang, et al.
Published: (2015)

Delay-Locked Loops with fast lock and phase error calibration
by: Chun Yi Kuo, et al.
Published: (2012)

Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop
by: You-Jen Wang, et al.
Published: (2010)

Design and Implementation of Delay-Locked Loops with Static Phase Error Calibration
by: Kuang-Fu Teng, et al.
Published: (2009)

Low Power Digital Phase Locked Loop with Self-Calibration
by: 張巧伶
Published: (2008)

A Digitally-Calibrated 65GHz Phase-Locked Loop
by: Jia-Hao Wu, et al.
Published: (2007)

All-Digital Phase-Locked Loops with Multiple-Delay Switching TDC
by: Lin, Cheng-Chung, et al.
Published: (2016)

A Sub-harmonically Injection Locked Phase Locked Loop with Fast Self-calibrated Timing Technique
by: Ze-Wai Lin, et al.
Published: (2016)

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops
by: Yu-Hsiang Huang, et al.
Published: (2009)

All Digitally controlled boost dc-dc converter with digitally delay lock loop based calibration
by: Jen Hou Wu, et al.
Published: (2013)

A Self - Calibrated Multiphase Delay - Locked Loop with Reuse SAR
by: Tzu-Hsiang Wang, et al.
Published: (2011)

A low-power fast-lock digital Delay-Locked Loop
by: Jyun-Cheng Lin, et al.
Published: (2007)

Digital Phase-Locked Loop With Background Supply Noise Calibration and Injection-Locked Clock Multiplier
by: Che-Wei Tien, et al.
Published: (2017)

All Digital Phase-Locked Loop With Programmable Phase Injection Locking
by: Kung, Fan-Hsiang, et al.
Published: (2009)

Delay-Locked Loop with Static Phase Error Calibration Based on Wide-Range Operation
by: Meng-Jhe Wu, et al.
Published: (2008)

A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier
by: Yo-hao Tu, et al.
Published: (2010)

Design of All-Digital Delay-Locked Loop with Hybrid Control Schemes
by: LIN,TENG-HUI, et al.
Published: (2019)

Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
by: Nasir Qassim
Published: (2005-01-01)

Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
by: Nasir Qassim
Published: (2005-01-01)

Analysis and Design of the Phase-Locked Loop with Fast-Digital-Calibration Charge Pump
by: Tsuen-Shiau Hwang, et al.
Published: (2010)

Multi-Function All-Digital Phase-Locked Loop
by: Chin, Yu-Tung, et al.
Published: (2016)

An All-Digital Phase-Locked Loop with Dynamic Phase Control for Fast Locking
by: Yun-Chen Chuang, et al.
Published: (2011)

A phase-locked loop with static phase error calibration
by: Po Tsun Wu, et al.
Published: (2011)

All-Digital Delay-Locked Loop with Supply Noise Suppression Technique
by: Chia-Hao Tsai, et al.
Published: (2009)

A Spur Cancellation Technique for Digital Multiplying Delay-Locked Loops
by: Yu-Hong Yang, et al.
Published: (2016)

Design and Implementation of Wide-Range Multi-phase Delay-Locked Loop
by: HONG-JIE GUO, et al.
Published: (2013)

Low-Power And Delay Monotonicity Digitally Controlled Oscillator For All-Digital Phase-Locked Loop Applications
by: Jhih-Ci Lan, et al.
Published: (2012)

Design and Application of CMOS Digital/Analog Delay-Locked Loops
by: Hsiang-Hui Chang, et al.
Published: (2004)

Design and Implementation of a Self-calibrated Technique for lowering Supply Noise in Delay-Locked Loop
by: Chien-Hsun Shih, et al.

Design and Implementation of Self-Calibrated Technique for Supply Voltage Variation and Noise for Delay-Locked Loop
by: Ming-Da Lai, et al.

Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop
by: Chung-Ting Lu, et al.
Published: (2007)

All Digital Phase-Locked Loop
by: Ya-lan Tsao, et al.
Published: (1996)

AN ALL DIGITAL PHASE LOCKED LOOP
by: Greco, J., et al.
Published: (1972)

A Wide-Range and Fast-Locking All-Digital Delay-Locked Loop Using a Phase-Tracing Delay Unit
by: Liang-Hsin Chen, et al.
Published: (2011)

Built-in test for performance characterization and calibration of phase-locked loops
by: Hsiao, Sen-Wen
Published: (2014)

An All-Digital Phase-Locked Loop Using a Time-Amplifier TDC with Calibration mechanism
by: 蕭彥邦
Published: (2014)

The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode
by: Chun-Yuan Chang, et al.
Published: (2011)

Performance enhancement techniques for low power digital phase locked loops
by: Elshazly, Amr
Published: (2012)