The X-Architecture Clock Routing With Considering Voltage-Island Placement
碩士 === 南華大學 === 資訊管理學系碩士班 === 97 === Considering the clock routing in a VLSI design system, clock delay, total wire length, and power consumption are three essential factors to impact the system performance. Different routing methods result the various total wire lengths and also make some influenc...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91563762267868066062 |