| Summary: | 碩士 === 南華大學 === 資訊管理學系碩士班 === 97 === Considering the clock routing in a VLSI design system, clock delay, total wire length, and power consumption are three essential factors to impact the system performance. Different routing methods result the various total wire lengths and also make some influences to the clock delay and power consumption. These are needed to pay attention in the VLSI routing techniques.
Clock skew is another important factor which is caused from different clock delays. An enough large clock skew can make very negative effects for the system performance. Therefore, the ideal objective of clock routing is that we expect to obtain an exact zero-skew clock tree to a VLSI system.
In the recent VLSI design environment, the voltage-island placement is most one of universal methodologies to save the power consumption in physical design. So, we cannot ignore the clock routing problem in the voltage-island placement environment. The main structure in this thesis is to solve the above clock routing problem in the voltage-island placement by using DME-XP routing method which is considering the post refinement of an extra flip. These methods are based on X-architecture and DME algorithm to make X-clock routing which can reduce total wire length and clock delay. Moreover, we apply the above X-clock routing in a multiple voltage-island placement to construct a zero-skew X-architecture clock tree. Then, we observe the effects in terms of clock delay, wire length, via cost, and power consumption from the results at different placements.
The proposed approach of DME-XP has applied to the IBM five benchmarks, which are partitioned into two- and three-voltage-island placements. According to our experiments, we compare their results with that of original placement using the same DME-XP clock routing. For the cases of two-voltage island, the clock delay and total wire length increase 12.8% and 0.3% on average, respectively; however, the via cost and power consumption reduce 0.74% and 14.2% on average, respectively. For the cases of three-voltage islands, the total wire length and via cost increase 0.3% and 0.24% on average, respectively; however, the clock delay and power consumption decrease up to 27.1% and 14.2% on average, respectively. From above comparisons, our X-clock routing approach is effective for a multi-voltage island placement, especially in the reduction of power consumption.
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