Design of Pipelined Circuits for Tolerating Multiple Timing Errors
碩士 === 國立東華大學 === 電子工程研究所 === 97 === In modern VLSI design, many large systems are realized with system-on-chip technology. As the technology of IC manufacturing advances, the number of transistors and the operating voltage keep decreasing. Hence, circuits are susceptible to noise, wire delay, soft...
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| Format: | Others |
| Language: | zh-TW |
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2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94632029539263269679 |