| Summary: | 碩士 === 國立東華大學 === 電子工程研究所 === 97 === In modern VLSI design, many large systems are realized with system-on-chip technology. As the technology of IC manufacturing advances, the number of transistors and the operating voltage keep decreasing. Hence, circuits are susceptible to noise, wire delay, soft errors, and other factors. Many of the problems are caused by timing errors. When data get into pipeline buffers due to environmental factors or process variation, timing errors may cause the circuit to operate incorrectly. One of solutions to these problems is error-resilient design. Error-resilient design for VLSI circuits can immediately detect and even correct errors. Such design is even more important when the system-on-chip era becomes practical for many applications.
This thesis proposes a new error-resilient design of pipelined circuits for tolerating multiple timing errors. We modify the pipeline buffer structure by adding appropriate control circuits to adjust to the timing errors. We have validated our technique by applying it to two example digital signal processing design: an FIR filter and an IIR filter. Finally, we have simulated the designs and implemented them with cell-based IC design flow. The results show that our designs add nearly no delay at a reasonable area cost.
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