| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 97 === As CMOS process technology advances, a single chip will accommodate more than one billion transistors. Traditionally, using bus as a communication interface is common, but will become a major performance bottleneck for system-on-chip designs. Therefore, network-on-chip architectures are proposed to deal with the issues.
Since the impact of process variation and defects increases with the feature size keeps shrinking, the routers and links of the network-on-chip designs are prone to permanent faults. Hence, the performance of the network-on-chip systems is not guaranteed. Therefore, fault tolerance has becomes one of the main issues for network-on-chip design.
In this thesis, we propose an approach to fault-tolerant routing by using specially designed routing tables for routers in network-on-chip architectures. Each router builds the routing table for whole network according to the status of adjacent routers, so that packets can transmit toward the destination from the source with faulty components. Furthermore, we split the network into several sub-networks to reduce the size of the routing table and achieve cost effectiveness.
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