A Data Flow Program Executor Study Based on the Petri Nets

碩士 === 國立彰化師範大學 === 電子工程學系 === 97 === A Petri net executor has been devised to own the performance of adaptive computing system that is implemented on the FPGA devices based on the data flow computing model. It is expected to break through the von Neumann bottleneck of the traditional computers base...

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Main Authors: Wei-Min Lin, 林偉民
Other Authors: Chi-Pan Hwang
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/78966346655667110444
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spelling ndltd-TW-097NCUE54280042015-10-13T12:05:45Z http://ndltd.ncl.edu.tw/handle/78966346655667110444 A Data Flow Program Executor Study Based on the Petri Nets 以派翠網為基礎之資料流程式執行器研究 Wei-Min Lin 林偉民 碩士 國立彰化師範大學 電子工程學系 97 A Petri net executor has been devised to own the performance of adaptive computing system that is implemented on the FPGA devices based on the data flow computing model. It is expected to break through the von Neumann bottleneck of the traditional computers based on control flow computing model. There a C compiler has been developed to generate an intermediate code represented by the Petri net based on the data flow model. It is downloaded to the Petri net executor to complete the program execution. The Petri net executor consists of triggering, scheduling, and executing hardware circuits that form an execution cycle. The realization of triggering and scheduling circuits is referred to the CAM technique. The functions of triggering circuit are token consuming, marking updating, triggerable-transitions matching, and exclusive transitions determination. The scheduling circuit generates a set of firable transitions refereeing the outputs from the triggering circuit and delivers to the executing circuit. The executing circuit is a group of precasted hardware computing circuits corresponding to the preseted operations of transitions to complete the program execution, specifically. Furthermore, the executing circuit reports the fired transitions to the triggering circuit to renew the execution cycle. There are fixed number of FPGA gates to realize the hardware circuits of Petri net executor. However, the adaptive computing system creates a disappointment which hardware gate counts depending on the program size are not easy to control. Owing to the limited computing circuits and cyclic operations of Petri net executor, its performance is inferior to adaptive computing system. But the performance of Petri net executor is far to surpass the traditional computing system based on the control flow operations that have been evaluated by the benchmark programs. Chi-Pan Hwang 黃其泮 2009 學位論文 ; thesis 41 zh-TW
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language zh-TW
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description 碩士 === 國立彰化師範大學 === 電子工程學系 === 97 === A Petri net executor has been devised to own the performance of adaptive computing system that is implemented on the FPGA devices based on the data flow computing model. It is expected to break through the von Neumann bottleneck of the traditional computers based on control flow computing model. There a C compiler has been developed to generate an intermediate code represented by the Petri net based on the data flow model. It is downloaded to the Petri net executor to complete the program execution. The Petri net executor consists of triggering, scheduling, and executing hardware circuits that form an execution cycle. The realization of triggering and scheduling circuits is referred to the CAM technique. The functions of triggering circuit are token consuming, marking updating, triggerable-transitions matching, and exclusive transitions determination. The scheduling circuit generates a set of firable transitions refereeing the outputs from the triggering circuit and delivers to the executing circuit. The executing circuit is a group of precasted hardware computing circuits corresponding to the preseted operations of transitions to complete the program execution, specifically. Furthermore, the executing circuit reports the fired transitions to the triggering circuit to renew the execution cycle. There are fixed number of FPGA gates to realize the hardware circuits of Petri net executor. However, the adaptive computing system creates a disappointment which hardware gate counts depending on the program size are not easy to control. Owing to the limited computing circuits and cyclic operations of Petri net executor, its performance is inferior to adaptive computing system. But the performance of Petri net executor is far to surpass the traditional computing system based on the control flow operations that have been evaluated by the benchmark programs.
author2 Chi-Pan Hwang
author_facet Chi-Pan Hwang
Wei-Min Lin
林偉民
author Wei-Min Lin
林偉民
spellingShingle Wei-Min Lin
林偉民
A Data Flow Program Executor Study Based on the Petri Nets
author_sort Wei-Min Lin
title A Data Flow Program Executor Study Based on the Petri Nets
title_short A Data Flow Program Executor Study Based on the Petri Nets
title_full A Data Flow Program Executor Study Based on the Petri Nets
title_fullStr A Data Flow Program Executor Study Based on the Petri Nets
title_full_unstemmed A Data Flow Program Executor Study Based on the Petri Nets
title_sort data flow program executor study based on the petri nets
publishDate 2009
url http://ndltd.ncl.edu.tw/handle/78966346655667110444
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