Design of 24 GHz Radar Integrated Circuits for Automotive Applications

碩士 === 國立中央大學 === 電機工程研究所 === 97 === The goal of the thesis is to design and implement a 24-GHz radar integrated circuits for the automotive radar applications. The radar integrated circuits have been designed and fabricated using WIN Semiconductors 0.5-?m E/D-PHEMT technology. First, the introducti...

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Bibliographic Details
Main Authors: Yi-shuo Wu, 吳翊碩
Other Authors: Hong-Yeh Chang
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/89601760925151925237
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Summary:碩士 === 國立中央大學 === 電機工程研究所 === 97 === The goal of the thesis is to design and implement a 24-GHz radar integrated circuits for the automotive radar applications. The radar integrated circuits have been designed and fabricated using WIN Semiconductors 0.5-?m E/D-PHEMT technology. First, the introduction and the theory of the oscillation are presented in chapter 1 and chapter 2, respectively. In chapter 3, a differential voltage controlled oscillation circuit is presented for K-band applications. The frequency of the differential VCO is from 18.8 to 27.5 GHz with a tuning bandwidth of 38% and an output power of higher than 4 dBm. The differential VCO demonstrates a figure-of-merit of -177 dBc/Hz. Besides, a user-defined varactor model has been presented in this chapter. The radar receiver and transmitter for the automotive radar applications are presented in chapter 4 and chapter 5, respectively. The radar transmitter consistes of a differential VCO and a two-stage power amplifier. The frequency of the radar transmitter is from 21.7 to 26 GHz with an output power of higher than 13 dBm. The radar receiver consistes of a differential VCO, a low noise amplifier, a buffer amplifier and a mixer. The RF frequency of the radar receiver is from 21.7 to 26 GHz with a conversion gain of higher than 9 dB and an IF frequency of from 0.1 to 3.4 GHz. The frequency synthesizer are presented using TSMC 0.18-?m CMOS peocess in chapter 6. The measured output frequency is locked at 1.472 GHz in close loop condition. Finally, the conclusion is given in chapter 7.