Bottom-up PLL Behavioral Modeling for Supply Noise Interactions and Yield Enhancement
博士 === 國立中央大學 === 電機工程研究所 === 97 === While CMOS sizes are shrinking rapidly, more and more ASIC applications adopt System-on-Chip (SOC) designs with nanometer technologies. Such analog/mixed-signal (AMS) designs with over million components lead serious integration issues during system verification....
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t5m73j |