| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 97 === With the advance process technology, process variation has more and more impacts on the device behaviors, which reduces the design yield dramatically. In order to solve this problem, design-for-yield (DFY) techniques are hot research topics recently. In the DFY design flow, the influence of process variation will be considered at early design stage to reduce the process variation impacts on the circuits. In this thesis, an automatic DFY approach is proposed for OTA circuits to reduce their process variation sensitivity. According to the relationship between transistor sizes and process variation sensitivity, the proposed flow automatically adjusts the transistor sizes to reduce process variation sensitivity of OTA circuits. This flow has been implemented by C language. With little changing on circuit performances, this program will find an optimal solution considering the process sensitivity and area overhead using simulated annealing algorithm. As shown in the experimental results, the proposed approach does reduce the process variation sensitivity and improve the design yield.
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